The present invention relates to a phase-locked loop circuit suitable for use in a magnetic-disk drive, a magnetic-tape drive or the like. In particular, the present invention relates to a digital phase-locked loop circuit for shortening the synchronization time and reducing steady-state phase jitters.
In recent years, digital-signal processing technologies are embraced in order to reduce the hardware size and to enhance the performance of an external storage device of a computer such as a magnetic-disk drive, a magnetic-tape drive or other storage-media drives. There are many examples in which the conventional analog circuit is implemented into a digital configuration. In particular, in the case of a phase-locked loop circuit (which is referred to hereafter as a PLL circuit), operating conditions can be set externally with ease. Accordingly, a PLL adopting a digital technique, which is referred to hereafter as a digital PLL, is proposed. For example, in the case of a PLL embracing an analog technique (referred to hereafter as an analog PLL) disclosed in Japanese Patent Laid-open No. 62-39915, the digital PLL is implemented by including digital circuits such as counters, processing circuits and delay elements in the configuration thereof as components.
A block diagram of a typical digital PLL circuit cited above is shown in FIG. 23. Reference numerals 101 and 102 shown in the figure each denote a counter whereas reference numeral 103 is a subtractor. Reference numeral 104 is a filter circuit. Reference numerals 73a to 73c and 74a to 74c each denote a delay element. Reference numerals 106 and 107 are a processor and a phase shift-oscillator respectively.
The frequency of a reference clock signal .phi..sub.0 used in the PLL circuit shown in the figure is set to a value several tens times the frequency of a peak pulse signal Pin, an input pulse signal obtained by typically reconstructing the wave form of a signal generated from a recording medium. Using the reference clock signal .phi..sub.0, the digital PLL circuit produces an output pulse signal Pout with a phase matching that of the input peak pulse signal Pin.
To be more specific, the frequency of the reference clock signal .phi..sub.0 is divided by the counter 101 to produce a variable pulse signal VP having a period equal to that of the input peak pulse signal Pin. The counter 102 measures the time gap between the input peak pulse signal Pin and the variable pulse signal VP in terms of pulses of the reference clock signal .phi..sub.0, outputting a phase difference X(u), a digital value representing the time gap. For example, if the input peak pulse signal Pin and the variable pulse signal VP have fixed periods equal to each other, the phase difference is also fixed and equal to an initial value. For example, if the initial difference in phase between the input peak pulse signal Pin and the variable pulse signal VP is equal to two periods (2 t.sub.0) of the reference clock signal .phi..sub.0 as shown in FIG. 24, the counter 102 outputs a value of 2 to represent the phase difference X(u). Hereafter, the value 2 may be expressed as `2`. The phase difference X(u) is supplied to the subtractor 103. The filter circuit 104 calculates a currently-to-be-held phase difference Y(u) in synchronization with the variable pulse signal VP. The subtractor 103 substracts the currently-to-be-held phase difference Y(u) from the phase difference X(u) to produce a phase error Z(u)=(X(u)-Y(u)). The phase error Z(u) is fed back to the filter circuit 104.
The phase error Z(u) is delayed by the delay elements 73a, 73b and 73c each time it is supplied to the filter circuit 104. In this way, last three pieces of phase error data Z(u) supplied so far are stored. The currently-to-be-held phase difference Y(u) is also delayed by the delay elements 74a, 74b and 74c each time it is produced by the processor 106. Similarly, last three pieces of phase difference data Y(u) generated so far are stored. The processor 106 calculates the currently-to-be-held phase difference Y(u) from the stored three pieces of phase error data Z(u) and the stored three pieces of phase difference data Y(u). The processing carried out by the processor 106 changes the computed value of the phase difference Y(u) until the phase error Z(u) becomes a zero, causing the phase difference Y(u) to finally settle at a fixed value.
When the phase difference Y(u) no longer changes and the value of the phase error Z(u) is zero, the phase difference Y(u) output by the filter circuit 104 is equal to the phase difference X(u), representing a difference in phase between the input peak pulse signal Pin and the variable pulse signal VP. Accordingly, the phase-shift oscillator 107 shifts the variable pulse signal VP by an amount corresponding to the value of the phase difference Y(u), generating an output pulse signal Pout having a phase matching that of the input peak pulse signal Pin.
The conventional technology, wherein components of the analog PLL circuit are replaced by digital devices, has been described so far. In the above description, however, only the configuration of the digital PLL circuit and an operation carried out only for coping with an initial difference in phase between the input peak pulse signal Pin and the output pulse signal Pout are covered. The description given so far does not include the following problems encountered in the conventional technology.
First of all, it takes a long time, in comparison to the analog PLL circuit, to generate an output pulse signal Pout as a control result for a detected phase difference. In the case of the analog PLL circuit, the phase of the output pulse signal Pout starts to change as soon as a phase difference is detected. In the digital PLL circuit, however, the control is inevitably delayed by at least about one period of the output pulse signal Pout because it takes time for the filter circuit 104 to perform processing and to pass control values. In the case of the control process for coping with an initial difference in phase disclosed in Japanese Patent Laid-open No. 62-39915 described above, an effect of the control delay is not seen clearly in a low speed lock-in PLL characteristic. However, the PLL characteristic which is required in a magnetic-disk drive or a magnetic tape-drive is a high speed lock-in PLL characteristic. In such a drive, the time to get the phase locked, which is referred to hereafter as an acquisition time, has to be shortened. In such a case, delayed control variables inevitably affect the PLL characteristic much. This is because a phase margin is eliminated by an internal delay occurring in the feedback loop. A comparison of phase margins between cases with and without an internal delay occurring in the feedback loop for an analog PLL circuit is shown in FIG. 25. With an internal delay occurring in the feedback loop, the PLL characteristic reveals undesired vibratory components due to the elimination of the phase margin as shown in FIG. 26, lengthening the acquisition time. Accordingly, the delay times of control variables impose constraints on the minimum length of the acquisition time, giving rise to a problem that the acquisition time cannot be further shortened.
Secondly, the period of the input peak pulse signal Pin is not necessarily an exact multiple of the period of the reference clock signal .phi..sub.0. Accordingly, the edges of the input peak pulse signal Pin vibrate relatively to those of the reference clock signal .phi..sub.0, causing steady-state phase errors known as steady-state jitters to appear in the output pulse signal Pout. In the conventional technology described above, a control variable is measured in terms of periods of the reference clock signal .phi..sub.0. Therefore, large steady-state jitters with an absolute value of up to one period are generated in the phase difference X(u) output by the counter 102. As a result, steady-state jitters having a magnitude in the range minus one period to plus one period of the reference clock signal .phi..sub.0 are seen in the output pulse signal Pout. In order to suppress the steady-state jitters, a reference clock signal .phi..sub.0 with a higher frequency is taken into consideration. To design a digital PLL circuit with the magnitude of its steady-state jitters kept in the range, say, -2 nsec to +2 nsec, however, it is necessary to set a reference clock signal .phi..sub.0 to a very high frequency of 500 MHz. At such a high frequency, it becomes extremely difficult to design digital circuits and, in addition, a problem of increased power consumption is also encountered as well.